ou might have heard about L1, L2, L3. These are different levels of the cache memory which give an extra hand to the CPU in order to fetch required data quickly. Each cache level has different size and varying speeds.
The researchers at MIT’s CSAIL think the “sizes of the caches represent a compromise between the needs of different kinds of programs, but it’s rare that they’re exactly suited to any one program.”
They have designed a new system called ‘Jenga’ which can create new “cache hierarchies” as per the requirement of a specific program. For instance, the system could even club cache levels into one big chunk or split them.
For a particular program, the related data might be present at different physical locations in the memory. It’s the job of Jenga to make the data reach the CPU as quickly as possible, and increase the overall speed.
During their tests, the researchers simulated a 36-core processor and achieved around 30% faster processing, when compared to its best-performing predecessor, and up to 85% reduction in power consumption.
However, these simulations are–far from actual implementation–only the digital outcomes based on the research. Performance improvement for real-world chips with a lesser number of cores is yet to be known. Another thing is how long it would take manufacturers to adopt such tech. To make their processors faster, the currently rely on shrinking the size of the transistors.
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